View YDA142_1183280.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

YDA142
D- 3D
DIGITAL INPUT STEREO 9.5W DIGITAL AUDIO POWER AMPLIFIER Overview
YDA142 (D-3D) is a 12V single supply voltage, high-efficiency digital audio power amplifier IC. An audio power amplifier with a maximum output of 9.5W (RL=8) x 2ch or 19W (RL=4) x 1ch can be configured with one chip. YDA142 has a "Pure Pulse Direct Speaker Drive Circuit" that directly drives speakers while reducing distortion of a pulse output signal and reducing noise on a signal, and it realizes the highest standard low distortion rate characteristics and low noise characteristics as compared with those of digital amplifier ICs in the same class. The circuit allows you to design a circuit with as few external parts as possible depending on use conditions because any filter is no longer required. It is possible to input a left-justified or right-justified 16bit/8bit digital audio signal of 32kHz, 44.1kHz, or 48kHz. In addition, YDA142 has a gain setting function in 32-level (analog setting) or 8-level (terminal setting). YDA142 has Over-current Protection function for speaker output terminals, IC Thermal Protection function, POP Noise Reduction function, and DC Input Detection function as well as Power-down function and Output Disable function.
Features
Maximum Output 9.5 Wx2ch (VDDP=12.0V, RL=8, THD+N=10%, MONO=L, GAIN[2:0]=H,L,L) 19 Wx1ch (VDDP=12.0V, RL=4, THD+N=10%, MONO=H, GAIN[2:0]=H,L,L) Efficiency 90 % (VDDP=12.0V, RL=8, Po=9.5W) Distortion Rate (THD+N) 0.05 % (VDDP=12.0V, RL=8, Po=1.0W, GAIN[2:0]=H,L,L) S/N Ratio 100dB (VDDP=12.0V, RL=8, Po=9.5W, GAIN[2:0]=H,L,L) Channel Separation Ratio -78dB (VDDP=12.0V) Supply voltage Range 9.0V to 13.5V 3-wire Digital Signal Input Fs: 32kHz/44.1kHz or 48kHz, Bits: 16bit or 18bit Gain Setting Function with GAIN[2:0] and GAINA terminal Power-down Function with SLEEPN terminal Output Mute Function with MUTEN terminal Monaural Output Function with MONO terminal Protection Functions (Over-current Protection, Thermal Protection, Clock Stop protection, Under-voltage Malfunction Prevention, DC Input Detection) Pop-noise Reduction Function Digital Input/BTL(Bridge-Tied Load) output Package Lead-free 52-pin SSOP (YDA142-EZ)
YDA142 CATALOG CATALOG No.:LSI-4DA142A20 2006.4
YDA142
Terminal configuration
<52-pin SSOP Top View>
2
YDA142
Terminal function
No. Name I/O Function Voltage tolerance LV LV LV LV HV HV HV HV HV HV LV LV LV LV LV LV LV LV LV LV LV LV HV HV HV HV HV HV HV HV HV LV LV 1 VREF O Analog reference voltage output 2 AVSS GND Ground terminal for analog circuits 3 VSSBGR GND Ground terminal for analog circuits 4 GAINA I Analog gain setting terminal 5 LINEOUTL O Lch Line output terminal 6 LINEOUTR O Rch Line output terminal 7 NC Normally, use this terminal in no-connection 8 PVSSR GND Ground terminal 9 PVSSR GND Ground terminal 10 PVDDR Power 12V power supply terminal 11 OUTPR O Rch positive side output terminal 12 OUTPR O Rch positive side output terminal 13 GND Ground terminal PVSSR 14 GND Ground terminal PVSSR 15 OUTMR O Rch negative side output terminal 16 OUTMR O Rch negative side output terminal 17 PVDDR Power 12V power supply terminal 18 GND Ground terminal PVSSR 19 GND Ground terminal PVSSR 20 NC Normally, use this terminal in no-connection 21 MUTEN I Output disable control terminal 22 MONO I Monaural control terminal 23 DVSS GND Ground terminal for digital circuits 24 SDIN I Serial audio data signal input 25 LRCLK I Serial LR clock signal input 26 SCLK I Serial bit clock signal input 27 MODE0 I Mode setting terminal 0 28 MODE1 I Mode setting terminal 1 29 GAIN0 I Volume setting terminal 0 30 GAIN1 I Volume setting terminal 1 31 GAIN2 I Volume setting terminal 2 32 FSSEL I Sampling frequency setting terminal 33 BITSEL I 16bit/18bit setting terminal 34 GND Ground terminal PVSSL 35 GND Ground terminal PVSSL 36 PVDDL Power 12V power supply terminal 37 OUTML O Lch negative side output terminal 38 OUTML O Lch negative side output terminal 39 GND Ground terminal PVSSL 40 GND Ground terminal PVSSL 41 OUTPL O Lch positive side output terminal 42 OUTPL O Lch positive side output terminal 43 PVDDL Power 12V power supply terminal 44 GND Ground terminal PVSSL 45 GND Ground terminal PVSSL 46 Normally, use this terminal in no-connection NC 47 Normally, use this terminal in no-connection NC 48 SLEEPN I Power-down control terminal 49 PROTN O/D Unusual condition warning output terminal 50 PVDDREG Power 12V power supply terminal for analog circuits 51 REFA O 5V reference voltage output terminal 52 DVDD I 5V reference voltage input terminal Note I: Input terminal, O: Output terminal, O/D: Open drain output terminal LV: Terminal for VREG power supply voltage range as input voltage range. HV: Terminal for VDDP power supply voltage range as input voltage range.
3
YDA142
Block diagram
4
YDA142
Description of operating functions
Serial Audio Interface
Sampling Frequency (Fs) Selection Input an audio signal using SCLK, LRCLK, and SDIN terminals. YDA142 supports three sampling frequencies (Fs): 32kHz, 44.1kHz, and 48kHz. Set the FSSEL terminal as follows in accordance with a Fs of a signal to use. At this time, use a frequency of 64Fs as a SCLK signal. FSSEL terminal setting FSSEL Sampling Frequency (Fs) L 44.1kHz, 48kHz H 32kHz Bit Number Selection YDA142 supports two bit widths: 16-bit and 18-bit. Set the BITSEL terminal as follows in accordance with a bit width to use. BITSEL terminal setting BITSEL Input Bit Number L 16 bits H 18 bits Format Selection YDA142 can select one out of three interface formats: Right-justified MSB first format, Left-justified MSB first format, and Left-justified (1bit delay) MSB first format. Set the MODE[1:0] as follows in accordance with a digital audio signal format to use. Fig.1 to Fig.3 shows the details of each format. MODE[1:0] terminal setting MODE1 MODE0 L L L H H L H H Input Signal Format Right-justified MSB first Left-justified MSB first Left-justified (1bit delay) MSB first Reserved
Right-justified MSB first
Fig.1 Right-justified MSB First Format
5
YDA142
Left-justified MSB first
Fig.2 Left-justified MSB First Format
Left-justified (1bit delay) MSB first
Fig.3 Left-justified (1bit delay) MSB First Format
6
YDA142
Gain setting function
The output gain for a digital amplifier and LINEOUTL(R) can be set by GAIN[2:0] terminal and GAINA terminal. Set the GAIN[2:0] as follows in accordance with a gain to use. With GAIN[2:0]= "L, L, L" the output gain of a digital amplifier and LINEOUTL(R) can be set by a GAINA terminal voltage. Set the GAINA terminal voltage as follows in accordance with a gain to use. When the GAINA terminal is not used, it is fixed to GND. GAIN[2:0] terminal gain setting GAIN2 GAIN1 GAIN0 L L L L H H H H L L H H L L H H L H L H L H L H Digital Amplifier Gain GAINA terminal priority 2dB 8dB 14dB 20dB 23dB 26dB 29dB LINEOUTL(R) Output Gain GAINA terminal priority -15dB -9dB -3dB 3dB 6dB 9dB 12dB
GAINA terminal Gain setting GAINA terminal voltage range Digital Amplifier LINEOUTL(R) (Voltage ratio to REFA voltage) Gain Output Gain 65.6% to 100.0% 32dB 15dB 64.0% to 67.2% 29dB 12dB 62.4% to 65.6% 26dB 9dB 60.8% to 64.0% 23dB 6dB 59.2% to 62.4% 20dB 3dB 57.6% to 60.8% 18dB 1dB 56.0% to 59.2% 16dB -1dB 54.4% to 57.6% 14dB -3dB 52.8% to 56.0% 12dB -5dB 51.2% to 54.4% 10dB -7dB 49.6% to 52.8% 8dB -9dB 48.0% to 51.2% 6dB -11dB 46.4% to 49.6% 4dB -13dB 44.8% to 48.0% 2dB -15dB 43.2% to 46.4% 0dB -17dB 41.6% to 44.8% -2dB -19dB 40.0% to 43.2% -4dB -21dB 38.4% to 41.6% -6dB -23dB 36.8% to 40.0% -8dB -25dB 35.2% to 38.4% -10dB -27dB 33.6% to 36.8% -12dB -29dB 32.0% to 35.2% -14dB -31dB 30.4% to 33.6% -16dB -33dB 28.8% to 32.0% -18dB -35dB 27.2% to 30.4% -20dB -37dB 25.6% to 28.8% -23dB -40dB 24.0% to 27.2% -26dB -43dB 22.4% to 25.6% -29dB -46dB 20.8% to 24.0% -32dB -49dB 19.2% to 22.4% -36dB -53dB 17.6% to 20.8% -40dB -57dB 0% to 19.2% Mute Mute A full scale of DAC is 1Vrms(2.8Vpp). This is assumed to be 0dB and the gain is set. For instance, when the gain of a digital amplifier is set to 14dB, and a full-scale signal of DAC is input, the digital amplifier output becomes 5Vrms(14Vpp).
7
YDA142
Analog Signal Output
When SLEEPN terminal is "H", L channel and R channel analog signals are output from LINEOUTL terminal and LINEOUTR terminal respectively, with an output gain designated by GAIN[2:0] terminal or GAINA terminal with respect to an input digital signal. The DC component is superimposed and output from LINEOUTL and LINEOUTR terminal. Therefore, the DC component is removed with the DC cut capacitor.
Digital Amplifier Output
When SLEEPN terminal is "H" and MUTEN terminal is "H", L channel signal is output between OUTPL terminal and OUTML terminal, with an output gain designated by GAIN[2:0] terminal or GAINA terminal with respect to an input digital signal. In addition, R channel signal is output between OUTPR terminal and OUTMR terminal. OUTPL and OUTPR terminal become a positive terminal, and OUTML and OUTMR terminals become a minus terminal, respectively. LC Filter YDA142 can be directly connected to a speaker without a LC filter because it adopts a modulation method capable of reducing speaker loss during no sound sufficiently by utilizing only inductance a speaker has. When a LC filter is not used, use a speaker with inductance of 20H or over at a carrier clock frequency of 500kHz. Use the following filter circuit when a LC filter is connected. At this time, use the following constants in accordance with speaker's impedance. Using these constants can make a low-pass filter with a cut-off frequency of 50kHz, Q=0.7 or so. The over current protection function might work by LC resonance when the LC filter is connected and uses, and operate IC without connecting the speaker. LC Filter constants RL L1 4 10H 8 22H 16 47H
C1 1.0F 0.47F 0.22F
Control Function
Sleep Function When SLEEPN terminal is "L", YDA142 enters Sleep Mode. The mode stops all the circuit functions including 5V Regulator and minimizes consumption current. At this time, the output stage of the digital amplifier is disabled and LINEOUTL and LINEOUTR terminals get undefined. And, PROTN terminal becomes "High-Z". Mute Function When MUTEN terminal is "L", YDA142 enters Mute Mode. In this mode, the output stage of the digital amplifier is disabled and LINEOUTL and LINEOUTR terminals output audio signals normally.
8
YDA142
Monaural Function When MONO terminal is "H", YDA142 enters Monaural Mode. In this mode, L channel input signal is output. The mode can output up to 19W power into a 4 load resistor by short-circuiting between OUTPL and OUTPR terminals and between OUTML and OUTMR terminals. In addition, LINEOUTL terminal outputs L channel input signals but LINEOUTR terminal gets undefined. Switch between Monaural Mode and Stereo Mode during SLEEP Mode or a power shutdown state.
Protection Function
YDA142 has the following protection functions: Over-current Protection function, Thermal Protection function, Clock Stop Protection function, Under-voltage Malfunction Prevention function, and DC Input Detection function. Over-current Protection Function This is a function to make the Over-current Protection Mode (disables the output stage of a digital amplifier in conjunction with "L" output to PROTN terminal) by detecting a short-circuiting (Ground short/Power supply short/Short between terminals) in the output stage of a digital amplifier. This mode can be cancelled by power supply shutdown or SLEEPN terminal "L" setting. In addition, the mode can be automatically resumed after the over-current detection by connecting PROTN terminal to SLEEPN terminal. Thermal Protection Function This is a function to make the Thermal Protection Mode (disables the output stage of a digital amplifier in conjunction with "L" output to PROTN terminal) by detecting extraordinary high temperature on YDA142. This mode can be cancelled by sufficient temperature decrease, power supply shutdown, or SLEEPN terminal "L" setting. In addition, the mode can be automatically resumed after the high temperature detection by connecting PROTN terminal to SLEEPN terminal. Clock Stop Protection Function This is a function to make the Clock Stop Protection Function (disables the output stage of a digital amplifier) when a SCLK signal frequency of the digital interface becomes a frequency lower than Stop Detection Frequency (FUFP). The mode can be cancelled by returning the carrier clock frequency to the normal value. Under-voltage Malfunction Prevention Function This is a function to make the Under Voltage Protection Function (disables the output stage of a digital amplifier in conjunction with setting "High-Z" state to PROTN terminal) when a voltage at 12V power supply terminal (PVDDREG) becomes lower than the Under Voltage Detection Threshold Voltage (VUVPL) or a voltage at 5V power supply terminal (DVDD) becomes lower than the Under Voltage Detection Threshold Voltage (VUVAL). The built-in 5V regulator is also disabled when a voltage at 12V power supply terminal becomes lower than the Threshold Voltage VUVPL. The mode can be cancelled when "L" is set to SLEEPN terminal or a voltage of each power supply terminal becomes higher than the Threshold Voltage (VUVPH, VUVAH).
9
YDA142
DC Input Detection Function This is a function to make the DC Input Protection Mode (disables digital amplifier output stage) when a digital input signal of the DC input detection voltage level (VDCIN) or more continues over the DC input detection time (TDCIN) without change of polarity. DC Input Protection Mode is cancelled when "L" is set to SLEEPN terminal or a digital input signal becomes lower than VDCIN or its polarity is changed.
5V Regulator Function
YDA142 outputs 5V (VREG) to REFA terminal when SLEEPN terminal is "H". Connect a capacitor of 0.1F or over to REFA terminal for stabilization. Connect the REFA terminal to DVDD terminal on a board. And, don't connect the REFA terminal to other terminals except DVDD terminal and YDA142 input terminals.
Pop-noise Reduction Function
Pop-noise Reduction Function works when powered on, when shut down, when SLEEP ON/OFF is switched, or when Mute ON/OFF is switched.
Power dissipation
The power dissipation of YDA142 is limited by unction temperature rating (125) and package thermal resistance (15.4/W: 4-layer board). The power dissipation and junction temperature can be found by the following formula. When used, take care so that the power dissipation and junction temperature do not exceed the absolute maximum ratings. Formula for the power dissipation Ploss = (Pout x Rpn / Rl) x 2 + Idc x Vdc
9.0
Ploss Pout Rpn Rl Idc
Vdc
: Power Dissipation (W) : Output Power (W) : 0.66 (constant) : Load Resistance () : 0.035(constant/at VDDP=12V) 0.028(constant/at VDDP=9V) 0.038(constant/at VDDP=13.5V) : Supply Voltage (V)
8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 10 20 30 40 50 60 70 80 90
Formula for the junction temperature Tj = Ploss x ja + Ta Ploss ja Ta : Power Dissipation (W) : 15.4(constant/package thermal resistance (/W), 4-layer board) : Ambient temperature ()
Package thermal resistance
The package (52SSOP) for YDA142 has a Thermal Pad for radiation on the surface. Use this Thermal Pad by soldering on a board. The package's thermal resistance is 15.4/W (4-layer board). This thermal resistance is a value measured under the following conditions: board size 136mmx85mm, 1st layer and 4th layer copper foil board density 154%, 2nd layer and 3rd layer copper foil board density 200%, no wind. In addition, the lower side pattern of the Thermal Pad is connected to all the layers in a board by through holes (0.4).
10
YDA142
Example of application circuit
ID C1 C2,C3 C4 C5 C6,C7,C8,C9 R1
Value 1F/16V 1F/16V 0.1F/16V 1F/25V 4.7F/25V 100k, 1/16W
Multilayer ceramic Multilayer ceramic Multilayer ceramic Multilayer ceramic Multilayer ceramic Chip Resistor
Element capacitor capacitor capacitor capacitor capacitor
11
YDA142
Electrical characteristics
Absolute Maximum Ratings Item Power Supply Terminal (VDDP) voltage range SLEEPN, PROTN terminal voltage range Control line terminal voltage range
Note 4) Note 1,2,3) Note 6)
Symbol VDDP VIN1 VIN3 VIN4 PD25 PD70 TJMAX TSTG
Min. -0.3 VSS-0.3 VSS-0.3 VSS-0.3
Max. 14.0 VDDP+0.3 VREG+0.3 VREG+0.3 6.4 3.6 125
Unit V V V V W W
Input/Output terminal voltage range Note 5) Power Dissipation (Ta=25, 4-layer board) Power Dissipation (Ta=70, 4-layer board) Junction Temperature Storage Temperature
Note 2) The voltage is based on VSS=0V.
-50
125
Note 1) VSS means AVSS, VSSBGR, DVSS, PVSSR, and PVSSL. Keep all the VSS terminals at the same potential. Note 3) The power supply terminal (VDDP) means PVDDREG, PVDDR, and PVDDL terminal. Note 4) The control input/output terminal means MUTEN, MONO, GAIN[2:0], MODE[1:0], BITSEL, FSSEL, SCLK, LRCLK, and SDIN terminal. Note 5) The input/output terminal means VREF and GAINA terminal. Note 6) Absolute Maximum Ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability.
Recommended operating condition Item Supply Voltage
Note 7)
Symbol VDDP Ta RLS RLM
Min. 9.0 -40 7.5 3.75
Typ. 12.0 25 8 4
Max. 13.5 85
Unit V
Operating Ambient Temperature Speaker Impedance (Stereo) Speaker Impedance (Mono)
Note 7) All the voltages are based on VSS=0V.
12
YDA142
DC Characteristics (VSS=0V, VDDP=12V0.5V, Ta=0 to 85, unless otherwise specified) Item REFA output terminal voltage DVDD input terminal voltage PROTN terminal Low level output voltage (IOL=1.6mA) SLEEPN terminal High level input voltage SLEEPN terminal Low level input voltage Control line input terminal High Level input voltage Control line input terminal Low Level input voltage PVDDREG terminal Startup threshold voltage PVDDREG terminal Shut-down threshold voltage DVDD terminal Startup threshold voltage DVDD terminal Shut-down threshold voltage DC input detection voltage level Consumption current (SLEEP Mode) Consumption current (Mute Mode) Consumption current (Silent, without filter) Symbol VREG VDVDD VOLP VIH1 VIL1 VIH2 VIL2 VUVPH VUVPL VUVAH VUVAL VDCIN ISLEEP IMUTE IDDD 8.0 7.6 3.7 3.3 18 1 20 40 2.2 0.8 2.2 0.8 Min. 4.5 4.5 Typ. 5 5 Max. 5.5 5.5 0.4 Unit V V V V V V V V V V V dBFS A mA mA
AC Characteristic (VSS=0V, VDDP=12V0.5V, Ta=0 to 85, unless otherwise specified) Item Carrier Clock Frequency (Fs=44.1kHz) Carrier Clock Frequency (Fs=48kHz, 32kHz) Clock stop detection SCLK signal frequency DC input detection time SCLK cycle time LRCLK setup time LRCLK hold time SDIN setup time SDIN hold time Symbol FCK FCK FUFP TDCIN TCYC TLRS TLRH TSDS TSDH 1.8 250 60 25 60 25 Min. Typ. 470 500 400 2 3.7 600 Max. Unit kHz kHz kHz s ns ns ns ns ns
13
YDA142
Analog Characteristics (VSS=0V, VDDP=12V, Ta=25, Frequency:1kHz, unless otherwise specified) Item Maximum output (Stereo) (THD+N=10%) Maximum output (Mono) (THD+N=10%) Voltage Gain (GAIN[2:0]=H,L,L) Total Harmonic Distortion Rate (Stereo) RL=8, PO=5W (BW: 20kHz) Total Harmonic Distortion Rate (Mono) (BW: 20kHz) Signal /Noise Ratio (BW: 20kHz A-Filter) Channel Separation Ratio Maximum Efficiency Output offset voltage RL=8, PO=9.5W RL=4, PO=9.5W RL=8, PO=9.5W, GAIN[2:0]=H,L,L SNR CS VO Conditions RL=8 PO RL=4 AV 19.0 20 0.05 THD+N 0.1 100 -78 90 20 % dB dB % mV W dB % Symbol Min. Typ. 9.5 Max. Unit W
Note) All the values of analog characteristics were obtained by using our evaluation circumstance. Depending upon parts and pattern layout to use, characteristics may be changed. 8 resistor and 30H coil are used as an output load in order to obtain various digital amplifier characteristics.
14
YDA142
Typical characteristics examples
Digital Amplifier Characteristics (VDDP=12V, Ta=25, RL=8+30H, Frequency=1kHz
Input level vs THD+N (Freq=1kHz, with 20kHz filter) 100 Lch Rch 10 THD+N [%]
Input signal frequency vs THD+N (Po=3.1W, with 20kHz filter) 100 Lch Rch 10 THD+N [%]
1
1
0.1
0.1
0.01 -60 -50 -40 -30 Input level [dBFS] -20 -10 0
0.01 100 1000 FREQ [Hz] 10000 100000
Noise FFT 0 -20 -40 Noise Level [dB] Lch Rch
Frequency Response 25 24 23 22 GAIN [dB] 21 20 19 18 17 16 15 Lch Rch
-60 -80 -100 -120 -140 -160 10 100 1000 FREQ [Hz] 10000 100000
10
100
1000 FREQ [Hz]
10000
100000
POWER vs Efficiency 100 90 Maximum output power [W] 80 70 Efficiency [%] 60 50 40 30 20 10 0 0 2 4 6 POWER [W] 8 10 12 8 16 14 12 10 8 6 4 2 0 8 9
Power supply voltage vs Maximum output power (THD+N=10%, GAIN[2:0]=HHH) 8 16
10
11
12
13
14
15
Power supply voltage [V]
Input level vs THD+N [MONO] (Freq=1kHz, with 20kHz filter, RL=4ohm) 100 NO.1 NO.2 10 THD+N [%]
Power supply voltage vs Maximum output power [MONO] (THD+N=10%, GAIN[2:0]=HHH) 30 25 20 15 10 5 0 4 8 16
1
0.1
0.01 -60 -50 -40 -30 Input level [dBFS] -20 -10 0
Maximum output power [W]
8
9
10
11
12
13
14
15
Power supply voltage [V]
15
YDA142
Package outline
16
YDA142
17
YDA142
Notice
The specifications of this product are subject to improvement changes without prior notice.

▲Up To Search▲

Price & Availability of YDA142

	To Download YDA142 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .